import os
import simsym
import symtypes
import errno
import model
import signal
import ptypes

IntArray = symtypes.tdict(simsym.SInt, ptypes.APREF)

class GENREGSET(simsym.SInt):
	def _declare_assumptions(self, assume):
		super(GENREGSET, self)._declare_assumptions(assume)
	@model.methodwrap()
	def INIT(self):
		self = 0
		return

class HardwareRegisters(simsym.tstruct(
		hwgenregs	= GENREGSET,
		hwstack		= IntArray,
		top		= simsym.SInt,
		hwstatwd	= ptypes.STATUSWD,
		hwip		= simsym.SInt,
		intflg		= simsym.SBool
		)):
	def _declare_assumptions(self, assume):
		super(HardwareRegisters, self)._declare_assumptions(assume)
	
	@model.methodwrap()
	def INIT(self):
		self.hwgenregs.INIT
		self.top = 0
		self.hwstatwd = 0
		self.hwip = 0
	
	@model.methodwrap(regs = GENREGSET)
	def SetGPRegs(self, regs):
		self.hwgenregs = regs
	
	@model.methodwrap()
	def GetGPRegs(self):
		return self.hwgenregs
	
	@model.methodwrap()
	def GetStackReg(self):
		return self.hwstack

	@model.methodwrap(stk = IntArray)
	def SetStackReg(self, stk):
		self.hwstack = stk

	@model.methodwrap()
	def GetIP(self):
		return self.hwip

	@model.methodwrap(ip = simsym.SInt)
	def SetIP(self, ip):
		self.hwip = ip

	@model.methodwrap()
	def GetStatWd(self):
		return self.hwstatwd

	@model.methodwrap(stwd = ptypes.STATUSWD)
	def SetStatWd(self, stwd):
		self.hwstatwd = stwd
	
	@model.methodwrap()
	def SetIntsOff(self):
		intflg = False
	
	@model.methodwrap()
	def SetIntsOn(self):
		intflg = True

model_class = HardwareRegisters
